1. Field of the Invention
The present invention relates to a memory test system for testing a semiconductor memory device, and more particularly to a pattern generator for use in conducting multi-bit tests of the semiconductor memory device.
The present application for a memory test system having a pattern generator for a multi-bit test, is based on and claims priority from Korean Patent Application No. 28409/1995 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
In the prior art, the testing time required to verify the integrity of a semiconductor memory device continues to increase with device density. Various testing techniques and algorithms have been proposed. In the basic data in-out testing, after one bit of test data is written-in and read-out from one memory cell, written-in data and the read-out data are compared in a logic comparator to determine whether the memory cell functions correctly or not. This type of testing is purely functional rather than parametric. Multi-bit testing has also been utilized to reduce testing time. In multi-bit testing, one bit of test data is simultaneously written to a plurality of memory cells and then stored data is simultaneously read out from the same set of memory cells. Peripheral test circuitry is provided on-board the memory chip to reduce testing time and expense. The read-out data is compared with written-in data in a comparator in the peripheral circuitry on-board the chip, and the result provided externally through an output buffer. The result is applied to the logic comparator of the test system. Finally, whether the memory cell functions correctly or not is determined by the external test system logic comparator. In this multi-bit testing, however, certain test bit patterns cannot be used as they lead to erroneous results. These limitations stem from the design of the pattern generator of prior art test systems, for reasons explained below. Moreover, where peripheral test circuits are provided on-board a memory device, external test systems must properly interface with the pattern generator and the internal test circuits to achieve correct results.
FIG. 1 is a block diagram illustrating a pattern generator and the logic comparator of a memory test system in the prior art. A technique shown in FIG. 1 is disclosed in U.S. Pat. No. 4,835,774 assigned to Advantest Corporation of Japan. FIG. 1 is composed of the pattern generator 11 for generating a test pattern and supplying the test pattern to a memory under test 13. A logic comparator 15 is arranged for comparing data output from the memory under test 13 to expected data "ED" from the pattern generator 11, to determine whether the memory cell works correctly in a data in-out memory test.
The pattern generator 11 of FIG. 1 is comprised of an address generator 21 for generating an address signal and supplying the generated address signal to the memory under test 13 through an address bus 12 to select a corresponding memory cell for a writing or read operation; a data generator 22 for continuously or repeatedly generating test data; a data memory 23 for storing certain types of test data; a multiplexer 26 for selecting between the output of the data generator 22 and an output of the data memory 23, so as to provide test data to be written in the memory under test 13 though a data terminal 14; a clock generator 24 for generating a clock signal and supplying the clock signal to the memory under test 13; and a control signal generator 25 for controlling the address generator 21, the data generator 22 and the clock generator 24.
The test system described in the aforementioned '774 patent to Advantest can be modified by altering (or replacing) the data memory 23 so that it provides an indication of the polarity of a memory cell corresponding to the address signal currently provided by the address generator 21. Each memory cell has a polarity determined as true or complement by the internal architecture of the chip such as a connection relation between a data line and the memory cell of the chip. Logic data "0" or "1" is output from the data memory 23 in dependence upon the polarity of the memory cell currently addressed. For example, if a least significant bit of the current address signal is a "0", the memory cell selected by the address signal has a true polarity. Otherwise, it has a complement polarity. (Of course, just the opposite arrangement may be true in another memory device.) Data identical to that applied through the data bus 14 is stored in the memory cell having the true polarity, while data opposite to data applied through the data bus 14 is stored in the memory cell having the complement polarity. For illustration it is assumed in this specification that data "0" is output from the data memory 23 in the case that the polarity of the memory cell is true, and that data "1" is output from the data memory 23 in the case that the memory cell has complementary polarity. For present purposes, the pattern generator circuit 11 as described in the '774 patent can also be modified to change the multiplexer 26 to an XOR gate, so as to complement the data generator bit when the current cell polarity is complementary. The complemented test bit is provided to the memory under test at node (data terminal) 14.
The test operation of a test system having the pattern generator 11 as shown in FIG. 1 will be described via various examples as follows. In a first case, after data "1" is written in a true memory cell, the memory cell is tested. In this case, data "1" is output from the data generator 22 under the control of a control signal generator 25, and data "0" is output from the data memory 23 (indicating a true polarity memory cell). Accordingly, an XOR gate 26 connected with output nodes of the data generator 22 and the data memory 23 supplies data "1" to the memory under test 13 through the data terminal 14, and simultaneously supplies data "1" as expected data "ED" to the external logic comparator 15. Expected data ED supplied to the logic comparator 15 is utilized as reference data for checking whether correct data is output from the memory under test 13 or not. In other words, if data "1" is output from the memory under test 13 (node 20), the memory under test 13 passes the test, at least with respect to the cell currently addressed. And, if data "0" is output from the memory under test 13, the memory under test 13 fails.
The second case is where a test data bit "0" is generated, and the current address again corresponds to a true polarity memory cell. Accordingly, data "0" is output from the data generator 22, and data "0" is output from the data memory 23. Consequently, XOR 26 supplies data "0" to the memory under test 13 through the data terminal 14 and simultaneously supplies data "0" to the logic comparator 15. The data "0" supplied from the data terminal 14 and data output from the memory under test 13 (node 20) are compared to each other in the logic comparator 15. If the data are identical to each other, the memory under test 13 passes, as before. If the data are not identical to each other, it is thereby determined that the memory under test 13 fails.
A third case is where a test bit "1" is generated for writing in a complement polarity memory cell. Thus, data "1" is output from the data generator 22, and data "1" is output from the data memory 23. Accordingly, XOR 26 supplies data "0" to the memory under test 13 and simultaneously supplies data "0" to the logic comparator 15 through the data terminal 14. Data "0" supplied through the data terminal 14 and data output from the memory under test 13 are compared to each other. It these two data are identical to each other, the memory under test 13 passes, and if these data are not identical to each other, it fails the test.
The fourth case is where a test bit "0" is generated for writing in the complement polarity memory cell. In this case, the "0" test bit is output from the data generator 22 under control of the control signal generator 25, and data "1" is output from the data memory 23 (indicating the complement polarity of the cell currently addressed). Accordingly, XOR 26 supplies a "1" to the memory under test 13 and simultaneously supplies a "1" to the logic comparator 15 though the data terminal 14. The logic "1" output from the data terminal 14 and data output from the memory under test 13 are again compared in the logic comparator 15. As before, if the two data are identical to each other, the memory passes as to functionality of the current cell. If the two output data are not identical to each other, the memory fails.
The testing techniques summarized above are useful even in the conventional pattern generator since a normal comparative operation is achieved. However, the circuits and methods described above cannot be applied directly to multi-bit testing procedures. In multi-bit testing, complications can raise depending upon the construction of the multi-bit logic circuits provided in the peripheral circuitry on-board the memory chip. Here for illustration we assume that the internal logic circuit is constructed so as to compare a plurality of bits, e.g. a byte, of data read-out from the memory cells. A logic "1" is output from the logic circuit in the case that the plurality of bits of data are all identical, and a logic "0" is output from the logic circuit in the case where one or more bits are not identical. In this example, test accuracy cannot be achieved in the second and third cases described above, as explained next.
Taking the second case as one example, data "0" is output from the data generator 22 under the control of the control signal generator 25, and data "0" is output from the data memory 23 responsive to the address signal of the address generator 21. These two data output from the data generator 22 and the data memory 23 are compared to each other in the XOR 26 as observed previously. The XOR 26 supplies data "0" to the memory under test 13 and simultaneously supplies data "0" to the logic comparator 15 as expected data ED through the data terminal 14. Expected data ED "0" and data output from the memory under test 13 at node 20 are compared to each other in the logic comparator 15. At this time, if the data are identical to each other, it is determined that the memory under test 13 passes and testing proceeds to the next data bit. If the two data are not identical to each other, it is determined that the memory under test 13 fails. However, in the case of the multi-bit test mode, since data "1" is output from the memory under test 13 in the case of passing (i.e. all the read-out bits are identical), and data "0" is output from the memory under test 13 in the case of failing, a correct data comparison cannot be achieved in logic comparator 15. This situation results in an erroneous test result, i.e. an indication that the memory chip is defective when in fact it is not. The third case is similar. Describing the third case in detail, in the multi-bit test mode, data "1" is output from the memory under test 13 in the case of passing, and data "0" is output from the memory under test 13 in the case of failing, again causing the erroneous test result in the logic comparator 15.